The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

May. 06, 2014
Applicants:

Jun Cheng, Beijing, CN;

Min Yan, Beijing, CN;

Mingbo Zhou, Beijing, CN;

Inventors:

Jun Cheng, Beijing, CN;

Min Yan, Beijing, CN;

Mingbo Zhou, Beijing, CN;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/04 (2014.01); H01L 21/50 (2006.01); H01L 21/66 (2006.01); H01L 25/03 (2006.01); H01L 25/075 (2006.01); H01L 33/00 (2010.01); H01L 23/00 (2006.01); H01L 33/62 (2010.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/042 (2013.01); H01L 21/50 (2013.01); H01L 22/12 (2013.01); H01L 22/14 (2013.01); H01L 22/22 (2013.01); H01L 24/95 (2013.01); H01L 25/03 (2013.01); H01L 25/0753 (2013.01); H01L 33/0095 (2013.01); H01L 33/62 (2013.01); H01L 25/50 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/10158 (2013.01); H01L 2933/0066 (2013.01);
Abstract

A manufacturing method includes: attaching a film onto a bonding surface of a wafer; performing laser cutting on the wafer to obtain a plurality of semiconductor light-emitting eutectic chips; attaching light-emitting surfaces of the plurality of eutectic chips on to an expansion film; detaching films from bonding surfaces of the plurality of eutectic chips; performing wafer expansion on the expansion film so that the plurality of eutectic chips have the same intervals as chip loading spaces on a substrate; attaching the expansion film onto a tray, and moving the tray so that positions of the plurality of eutectic chips correspond to that of the chip loading spaces; moving the tray so that the plurality of eutectic chips approach the chip loading spaces on the substrate; and embedding the plurality of eutectic chips into the chip loading spaces so that the plurality of eutectic chips are electrically connected to the substrate.


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