The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2017
Filed:
Jun. 30, 2015
Applicant:
Sunasic Technologies, Inc., New Taipei, TW;
Inventors:
Chi-Chou Lin, New Taipei, TW;
Zheng-Ping He, Taipei, TW;
Assignee:
Sunasic Technologies Inc., New Taipei, TW;
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 21/768 (2006.01); H01L 21/78 (2006.01); G06F 3/044 (2006.01);
U.S. Cl.
CPC ...
H01L 24/06 (2013.01); G06F 3/044 (2013.01); H01L 21/7685 (2013.01); H01L 21/76802 (2013.01); H01L 21/76885 (2013.01); H01L 21/78 (2013.01); H01L 23/3171 (2013.01); H01L 2224/0912 (2013.01);
Abstract
A chip with I/O pads on the peripheries and a method making the chip is disclosed. The chip includes: a substrate; at least two metal layers, formed above the substrate, each metal layer forming a specific circuit, wherein two adjacent metal layers are separated by an inter-metal dielectric layer; and a passivation layer, formed on a top side of the chip. By changing the I/O pad from the top of the chip to the peripheries, the extra thickness of the packaged chip caused by wire bonding in the prior arts can be reduced.