The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Nov. 21, 2013
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Kwang-Hyun Kim, Gyeonggi-do, KR;

Kang-Youl Lee, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/02 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G11C 29/023 (2013.01); G11C 7/106 (2013.01); G11C 7/1039 (2013.01); G11C 7/1066 (2013.01); G11C 7/222 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); G11C 29/028 (2013.01); G11C 2207/2281 (2013.01);
Abstract

A semiconductor device includes a memory region suitable for providing a plurality of read data in parallel at every read operation cycle, an output path suitable for outputting the plurality of read data at a set time in response to an internal clock and one or more internal control signals at the every read operation cycle, and an output path control unit suitable for generating the internal control signal in response to a read command and generating the internal clock in response to a system clock, wherein a shifting time of a first edge of the internal clock is adjusted by a set level at the every read operation cycle during a test mode.


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