The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Dec. 21, 2015
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Tomoaki Nakano, Yokohama, JP;

Shigefumi Irieda, Yokohama, JP;

Masashi Yoshida, Yokohama, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/12 (2006.01); G11C 11/56 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5628 (2013.01); G11C 16/10 (2013.01); G11C 16/04 (2013.01); G11C 16/0483 (2013.01); G11C 16/12 (2013.01); G11C 16/3427 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes a first memory cell, a second memory cell, and a third memory cell, a first word line coupled to the first memory cell, the second memory cell, and the third memory cell, a first bit line coupled to the first memory cell, a second bit line coupled to the second memory cell, and a third bit line coupled to the third memory cell. A first voltage, a second voltage, and a third voltage are sequentially applied to the first word line, and a fourth voltage is applied to the first bit line when the first voltage is applied to the first word line, applied to the second bit line when the second voltage is applied to the first word line, and applied to the third bit line when the third voltage is applied to the first word line.


Find Patent Forward Citations

Loading…