The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

May. 16, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Dexter Tamio Chun, San Diego, CA (US);

Vaishnav Srinivas, San Diego, CA (US);

David Ian West, San Diego, CA (US);

Deepti Vijayalakshmi Sriramagiri, San Diego, CA (US);

Jungwon Suh, San Diego, CA (US);

Jason Thurston, Raleigh, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G11C 5/14 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G11C 5/147 (2013.01); G06F 11/076 (2013.01); G06F 11/1004 (2013.01); G01R 31/3171 (2013.01); G01R 31/31709 (2013.01);
Abstract

Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.


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