Reorder buffer permitting parallel processing operations with repair on ordering hazard detection within interconnect circuitry

Abstract

A system-on-chip integrated circuitincludes interconnect circuitryfor communicating transactions between transaction sources and transaction destinations. A reorder bufferserves to buffer and permit reordering of access transactions received from the transaction sources. Processing circuitry performs processing operations in parallel upon a given access transaction taken from the reorder buffer. Hazard detection and repair circuitry serves to detect an ordering hazard arising between the processing operations and if necessary cancel and repeat that processing operation. The access transactions and the reorder buffer are such that access transactions other than the access transaction for which a hazard has been detected may proceed independently of the necessity to cancel and repair that transaction thereby reducing the cost associated with cancelling and repair.