The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Jun. 29, 2012
Applicants:

Cissy Yuan, Shenzhen, CN;

Erkun Mao, Shenzhen, CN;

Qian Chen, Shenzhen, CN;

Jian Wang, Shenzhen, CN;

Xuehong Tian, Shenzhen, CN;

Daibing Zeng, Shenzhen, CN;

Wanting Tian, Shenzhen, CN;

Inventors:

Cissy Yuan, Shenzhen, CN;

Erkun Mao, Shenzhen, CN;

Qian Chen, Shenzhen, CN;

Jian Wang, Shenzhen, CN;

Xuehong Tian, Shenzhen, CN;

Daibing Zeng, Shenzhen, CN;

Wanting Tian, Shenzhen, CN;

Assignee:

ZTE Corporation, Shenzhen, Guangdong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/0864 (2016.01); G06F 12/0893 (2016.01); G06F 12/0862 (2016.01); G06F 12/0831 (2016.01); G06F 17/30 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0864 (2013.01); G06F 12/0831 (2013.01); G06F 12/0862 (2013.01); G06F 12/0893 (2013.01); G06F 17/30982 (2013.01); G06F 2212/1012 (2013.01); G06F 2212/601 (2013.01); G06F 2212/6032 (2013.04); G06F 2212/621 (2013.01);
Abstract

The disclosure discloses an intelligence cache and an intelligence terminal, wherein the intelligence cache comprises: a general interface, configured to receive configuration information and/or control information, and/or data information from a core a bus, and return target data; a software define and reconfiguration unit configured to define a memory as a required cache memory according to the configuration information; a control unit, configured to control writing and reading of the cache memory and monitor instructions and data streams in real time; a memory unit, composed of a number of memory modules and configured to cache data; the required cache memory is formed by memory modules according to the definition of the software define and reconfiguration unit; and an intelligence processing unit, configured to process input and output data and transfer, convert and operate on data among multiple structures defined in the control unit. The disclosure can realize an efficient memory system according to the operating status of software, the features of tasks to be executed and the features of data structures through the flexible organization and management by the control unit and the close cooperation of the intelligence processing unit.


Find Patent Forward Citations

Yuan, Cissy. (2017). Intelligence cache and intelligence terminal (U.S. Patent No. 9632940). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9632940

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…