The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Nov. 06, 2014
Applicant:

Silicon Motion, Inc., Jhubei, Hsinchu County, TW;

Inventors:

Chien-Cheng Lin, Yilan, TW;

Chia-Chi Liang, Taichung, TW;

Chang-Chieh Huang, Zhubei, TW;

Jie-Hao Lee, Kaohsiung, TW;

Assignee:

SILICON MOTION, INC., Jhubei, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/14 (2006.01); G06F 12/02 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); G06F 12/121 (2016.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1469 (2013.01); G06F 11/1072 (2013.01); G06F 12/0246 (2013.01); G06F 12/121 (2013.01); G11C 29/52 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/69 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7202 (2013.01); G06F 2212/7203 (2013.01); G06F 2212/7209 (2013.01); G11C 2029/0411 (2013.01); Y02B 60/1225 (2013.01);
Abstract

A data storage device with flash memory and a flash memory control method are disclosed, which upload the physical-to-logical address mapping information of one block to the flash memory section by section. A microcontroller is configured to allocate a flash memory to provide a first run-time write block. Between a first write operation and a second write operation of the first run-time write block, the microcontroller updates a logical-to-physical address mapping table in accordance with just part of a first physical-to-logical address mapping table. The logical-to-physical address mapping table is provided within the flash memory. The first physical-to-logical address mapping table is established in the random access memory to record logical addresses corresponding to physical addresses of one block.


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