The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Feb. 17, 2014
Applicant:

Sharp Kabushiki Kaisha, Osaka-shi, Osaka, JP;

Inventors:

Yasushi Sasaki, Osaka, JP;

Yuhichiroh Murakami, Osaka, JP;

Shuji Nishi, Osaka, JP;

Takahiro Yamaguchi, Osaka, JP;

Makoto Yokoyama, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01); G06F 1/10 (2006.01); G11C 19/28 (2006.01); G06F 1/26 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); G06F 1/26 (2013.01); G11C 19/28 (2013.01); G09G 3/3677 (2013.01); G09G 2310/0286 (2013.01);
Abstract

A shift register is configured by connecting unit circuitsin multiple stages. An output transistor Trswitches between whether or not to output a clock signal CKA in accordance with a gate potential. A drain terminal of an initialization transistor Tra is connected to a gate terminal of the Tr, and a source terminal thereof is connected to an output terminal OUT or a clock terminal CKA. The source terminal of the Tra is connected to a node which has a low-level potential at the time of initialization and has a potential at the same level as the clock signal when the clock signal having a high-level potential is outputted. Thus, at the time of outputting the clock signal having the high-level potential, application of a high voltage between the source and the drain of the Tra is prevented, and degradation and breakdown of the initialization transistor are prevented.


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