The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Oct. 09, 2013
Applicant:

Scaleo Chip, Valbonne, Sophia Antipolis, FR;

Inventors:

Cédric Chillie, Tanneron, FR;

Tatiana Kauric, Vallauris, FR;

Assignee:

Silicon Mobility, Valbonne/Sophia-Anitpolis, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); H04L 1/00 (2006.01); G06F 11/07 (2006.01); G01R 31/3187 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31715 (2013.01); G01R 31/31713 (2013.01); H04L 1/00 (2013.01); G01R 31/3187 (2013.01); G06F 11/07 (2013.01);
Abstract

An input/output (IO) pad circuitry for integrated circuits (ICs) that is equipped with safety monitoring and control circuits to ensure that signals provided to/from the IO pad behave correctly. The IO pad circuitry allows monitoring of the IO pad signals, the detection of an undesired behavior, e.g., a wrong signal level or a wrong waveform. Furthermore, depending on a selected safety mode, a correction of the IO pad signals by overriding the monitored signal is further achieved. When in full safe mode, signals are provided as required, while in a partial safe mode only certain signals are provided depending on the status. A grouped safe mode allows providing a safe status to a group of IO pads using a single control. A monitoring circuitry between a plurality of input signals to an IC pad is also provided.


Find Patent Forward Citations

Chillie, Cédric. (2017). Io pad circuitry with safety monitoring and control for integrated circuits (U.S. Patent No. 9632139). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9632139

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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