The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2017
Filed:
Jan. 26, 2016
Applicant:
Avnera Corporation, Beaverton, OR (US);
Inventors:
Jianping Wen, Beaverton, OR (US);
Ali Hadiashar, Portland, OR (US);
Eric King, San Jose, CA (US);
David Entrikin, Portland, OR (US);
Wai Lang Lee, Austin, TX (US);
Assignee:
AVNERA CORPORATION, Beaverton, OR (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 3/00 (2006.01);
U.S. Cl.
CPC ...
H03M 3/496 (2013.01); H03M 3/32 (2013.01);
Abstract
Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.