The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Sep. 18, 2015
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Satoshi Sakurai, San Carlos, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/66 (2006.01); H03M 1/12 (2006.01); H03K 19/018 (2006.01); G11C 27/02 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1245 (2013.01); G11C 27/02 (2013.01); H03K 19/01812 (2013.01); H03M 1/12 (2013.01);
Abstract

Systems and methods for load current compensation for analog input buffers. In various embodiments, an input buffer may include a first transistor (Q) having a collector terminal coupled to a power supply node and a base terminal coupled to a first input node (v); a second transistor (Q) having a collector terminal coupled to an emitter terminal of the first transistor (Q); a third transistor (Q) having an emitter terminal coupled to an emitter terminal of the second transistor (Q) and to a ground node, a collector terminal coupled to a current source (I), and a base terminal coupled the collector terminal and to a base terminal of the second transistor (Q); and a capacitor (C) coupled to the base terminals of the second and third transistors (Qand Q) and to a second input node (v), wherein the first and second input nodes (vand v) are differential inputs.


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