The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Jun. 24, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Palkesh Jain, Bangalore, IN;

Keith Alan Bowman, Morrisville, NC (US);

Virendra Bansal, Bangalore, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/08 (2006.01); H03K 3/03 (2006.01); H03K 5/135 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0802 (2013.01); H03K 3/0315 (2013.01); H03K 5/135 (2013.01); H03K 2005/00019 (2013.01);
Abstract

An adaptive clock distribution (ACD) system with a voltage tracking clock generator (VTCG) is disclosed. The ACD system includes a tunable-length delay (TLD) circuit, to generate a TLD clock by adding a preselected delay to a root clock, and a voltage droop detector for detecting a voltage droop in a supply voltage. The VTCG is configured to generate a VTCG clock, wherein a frequency of the VTCG clock is finely tuned to one of two or more values to correspond to a magnitude of the supply voltage during the voltage droop. A clock selector selects the VTCG clock as an ACD clock to be provided to an electronic circuit during the voltage droop and the TLD clock as the ACD clock when there is no voltage droop detected.


Find Patent Forward Citations

Loading…