The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Feb. 15, 2016
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Osamu Ozawa, Kanagawa, JP;

Masashi Horiguchi, Kanagawa, JP;

Yuichi Okuda, Kanagawa, JP;

Akihito Anzai, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 5/32 (2006.01); H05K 1/18 (2006.01); H02H 7/20 (2006.01); H03B 5/36 (2006.01);
U.S. Cl.
CPC ...
H03B 5/32 (2013.01); H02H 7/20 (2013.01); H03B 5/364 (2013.01); H05K 1/181 (2013.01); H03B 2200/0088 (2013.01); H03B 2202/03 (2013.01); H03B 2202/082 (2013.01); H03B 2202/084 (2013.01); H05K 2201/10075 (2013.01);
Abstract

A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.


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