The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

May. 04, 2016
Applicant:

Sentinel Connector Systems, Inc., York, PA (US);

Inventors:

Brett D. Robinson, Chino, CA (US);

Justin Wagner, York, PA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 13/658 (2011.01); H01R 13/6581 (2011.01); H01R 13/6474 (2011.01); H01R 24/64 (2011.01); H01R 107/00 (2006.01); H01R 13/66 (2006.01);
U.S. Cl.
CPC ...
H01R 13/6581 (2013.01); H01R 13/6474 (2013.01); H01R 24/64 (2013.01); H01R 13/6658 (2013.01); H01R 2107/00 (2013.01); Y10T 29/49165 (2015.01);
Abstract

A method of manufacturing a high speed jack, the method including the steps of forming a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug, forming a shielding case surrounding the housing, forming a top layer of a substrate, a first shielding layer on a first side of the top layer in the substrate, a second shielding layer adjacent the first shielding layer in the substrate, and forming a bottom layer adjacent to the second shielding layer, forming a plurality of first vias extending through the substrate with each first via being configured to accommodate a pin on the housing, forming a plurality of second vias extending through the substrate with each second via being configured to accommodate a pin on the housing.


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