The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Oct. 08, 2014
Applicant:

Lg Innotek Co., Ltd., Seoul, KR;

Inventors:

Eun Ju Hong, Seoul, KR;

Jung Hun Oh, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
F21S 6/00 (2006.01); H01L 33/62 (2010.01); F21V 3/04 (2006.01); F21K 9/00 (2016.01); F21V 8/00 (2006.01); H01L 33/08 (2010.01); H01L 23/00 (2006.01); F21Y 105/00 (2016.01); H01L 33/20 (2010.01); H01L 33/38 (2010.01); F21Y 101/00 (2016.01);
U.S. Cl.
CPC ...
H01L 33/62 (2013.01); F21K 9/00 (2013.01); F21V 3/049 (2013.01); F21V 3/0472 (2013.01); G02B 6/0011 (2013.01); H01L 24/14 (2013.01); H01L 33/08 (2013.01); F21Y 2101/00 (2013.01); F21Y 2105/00 (2013.01); H01L 33/20 (2013.01); H01L 33/38 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/181 (2013.01);
Abstract

Embodiments provide a light emitting device including a substrate, a light emitting structure disposed under the substrate, the light emitting structure including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, a sub-mount, first and second metal pads disposed on the sub-mount and electrically spaced apart from one another, a one first bump disposed between the first conductive semiconductor layer and the first metal pad and a second bump located between the second conductive semiconductor layer and the second metal pad. A plurality of active areas in which The first semiconductor layer and the active layer are disposed are spaced apart from one another when viewed in plan.


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