The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Jul. 18, 2016
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventor:

Detlef Wilhelm, Regensburg, DE;

Assignee:

INFINEON TECHNOLOGIES AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/148 (2006.01); H01L 21/00 (2006.01); H01L 21/20 (2006.01); H01L 23/48 (2006.01); H01L 29/66 (2006.01); H01L 29/94 (2006.01); H01L 27/06 (2006.01); H01L 21/265 (2006.01); H01L 21/02 (2006.01); H01L 21/3205 (2006.01); H01L 21/8234 (2006.01); H01L 27/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66181 (2013.01); H01L 21/02107 (2013.01); H01L 21/265 (2013.01); H01L 21/32051 (2013.01); H01L 21/823475 (2013.01); H01L 27/0629 (2013.01); H01L 27/0805 (2013.01); H01L 29/94 (2013.01);
Abstract

A circuit arrangement may be provided. The circuit arrangement may include a semiconductor substrate including a first surface, a second surface opposite the first surface, and a first doped region of a first conductivity type extending from the first surface into the semiconductor substrate. The circuit arrangement may include at least one capacitor including a first electrode including a doped region of the first conductivity type extending from the second surface into the semiconductor substrate, a dielectric layer formed over the first electrode extending from the second surface away from the semiconductor substrate, and a second electrode formed over the dielectric layer opposite the first electrode. The circuit arrangement may further include at least one semiconductor device monolithically integrated in the semiconductor substrate. The first doped region of the first conductivity type may extend from the first surface into the semiconductor substrate to form an electrically conductive connection with the first electrode.


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