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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9627487 B1

PDFFull Text
Date of Patent:
Apr. 18, 2017

Filed:

Mar. 05, 2014

Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device

Applicant:

Sumitomo Electric Industries, Ltd., Osaka-shi, JP;

Inventors:

Kenji Hiratsuka, Osaka, JP;

Yu Saitoh, Osaka, JP;

Takeyoshi Masuda, Osaka, JP;

Assignee:

Sumitomo Electric Industries, Ltd., Osaka-shi, JP;

Attorneys:

Venable LLP

Michael A. Santori

Primary Examiner:

Allan R Wilson

Int. Cl.
CPC ...
H01L 29/16 (2006.01); H01L 21/3065 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/04 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 29/739 (2006.01); H01L 29/04 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); H01L 21/02238 (2013.01); H01L 21/02255 (2013.01); H01L 21/049 (2013.01); H01L 21/0475 (2013.01); H01L 21/3065 (2013.01); H01L 21/3081 (2013.01); H01L 21/31111 (2013.01); H01L 29/4236 (2013.01); H01L 29/42368 (2013.01); H01L 29/66068 (2013.01); H01L 29/7397 (2013.01); H01L 29/7813 (2013.01); H01L 29/045 (2013.01);
Abstract

A silicon carbide substrate has first to third semiconductor layers. The first and third semiconductor layers have a first conductivity type, and the second semiconductor layer has a second conductivity type. A trench has a bottom surface and first to third side surfaces, the bottom surface being constituted of the first semiconductor layer, the first to third side surfaces being respectively constituted of the first to third semiconductor layers. A gate insulating film having a bottom portion and a side wall portion is provided on the trench. The bottom portion has a minimum thickness d. A portion of the side wall portion on the second side surface has a minimum thickness d. A portion, connected to the bottom portion, of the side wall portion on the first side surface has a thickness d. Moreover, d>dand d>dare satisfied.

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