The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Mar. 15, 2016
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Myung-Ok Kim, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 21/764 (2006.01); H01L 27/108 (2006.01); H01L 23/535 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7682 (2013.01); H01L 21/28518 (2013.01); H01L 21/764 (2013.01); H01L 21/7685 (2013.01); H01L 21/76805 (2013.01); H01L 21/76826 (2013.01); H01L 21/76831 (2013.01); H01L 21/76855 (2013.01); H01L 21/76879 (2013.01); H01L 21/76895 (2013.01); H01L 23/5222 (2013.01); H01L 23/535 (2013.01); H01L 27/10855 (2013.01); H01L 27/10885 (2013.01); H01L 27/10888 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method of fabricating a semiconductor device and a semiconductor device formed by the method. The method includes form a stack conductive structure by stacking a first conductive pattern and an insulation pattern over a substrate; forming a sacrificial pattern over sidewalls of the stack conductive structure; forming a second conductive pattern having a recessed surface lower than a top surface of the stack conductive structure; forming a sacrificial spacer to expose sidewalls of the insulation pattern by removing an upper portion of the sacrificial pattern; reducing a width of the exposed portion of the insulation patters; forming a capping spacer to cap the sidewalls of the insulation pattern having the reduced width over the sacrificial spacer; and forming an air gap between the first conductive pattern and the second conductive pattern by converting the sacrificial spacer to volatile byproducts.


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