The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Feb. 06, 2014
Applicant:

Surecore Limited, Leeds, GB;

Inventor:

Andrew Pickering, Rugby, GB;

Assignee:

SURECORE LIMITED, Leeds, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 14/00 (2006.01); G11C 8/14 (2006.01); G11C 11/412 (2006.01); G11C 11/418 (2006.01); G11C 11/413 (2006.01); G11C 11/417 (2006.01); G11C 11/404 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0063 (2013.01); G11C 8/14 (2013.01); G11C 11/404 (2013.01); G11C 11/412 (2013.01); G11C 11/413 (2013.01); G11C 11/417 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01);
Abstract

There is provided a memory unit that comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to a first local bit line and a second local bit line by respective first and second access transistors, and each memory cell being associated with a word line configured to control the first and second access transistors of the memory cell. The first and second local bit lines of each memory cell group being operatively connected to respective first and second column bit lines by respective first and second group access switches, the first group access switch being configured to be controlled by the second column bit line, and the second group access switch being configured to be controlled by the first column bit line.


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