The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Dec. 12, 2014
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Chul-Moon Jung, Gyeonggi-do, KR;

Saeng-Hwan Kim, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/408 (2006.01); G11C 29/00 (2006.01); G11C 11/406 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4085 (2013.01); G11C 11/408 (2013.01); G11C 11/40611 (2013.01); G11C 29/76 (2013.01); G11C 29/783 (2013.01);
Abstract

An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.


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Jung, Chul-Moon. (2017). Address generation circuit and memory device including the same (U.S. Patent No. 9627032). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9627032

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