The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Jul. 20, 2015
Applicant:

AU Optronics Corp., Hsin-Chu, TW;

Inventors:

Wei-Li Lin, Hsin-Chu, TW;

Che-Wei Tung, Hsin-Chu, TW;

Chia-Heng Chen, Hsin-Chu, TW;

Assignee:

AU OPTRONICS CORP., Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01); G09G 3/20 (2006.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G09G 3/20 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0214 (2013.01); G09G 2320/0219 (2013.01); G11C 19/28 (2013.01);
Abstract

A shift register includes a plurality of stages of shift register circuit. Each stage of shift register circuit includes a first switch, an input circuit, a pull-down circuit, and a pull-down voltage regulator circuit. The first switch is used to output a scan signal according to a voltage level of a node and a clock signal. The input circuit is used to pull up the voltage level of the node according to a signal from a previous M-th stage of shift register circuit. The pull-down circuit is used to pull down the voltage level of the node according to the clock signal and a signal from a following L-th shift register circuit and reduce current leakage at the node. The pull-down voltage regulator circuit is used to pull down the voltage levels of the node and the scan signal according to the voltage level of the node.


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