The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Jul. 08, 2014
Applicants:

Gaurav Chawla, Austin, TX (US);

Robert Wayne Hormuth, Cedar Park, TX (US);

Michael Karl Molloy, Round Rock, TX (US);

Shyam T. Iyer, Austin, TX (US);

Inventors:

Gaurav Chawla, Austin, TX (US);

Robert Wayne Hormuth, Cedar Park, TX (US);

Michael Karl Molloy, Round Rock, TX (US);

Shyam T. Iyer, Austin, TX (US);

Assignee:

Dell Products L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 13/10 (2006.01); G06F 13/28 (2006.01); G06F 13/42 (2006.01); G06F 9/455 (2006.01); G06F 9/44 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4027 (2013.01); G06F 9/45558 (2013.01); G06F 13/102 (2013.01); G06F 13/28 (2013.01); G06F 13/4221 (2013.01); G06F 9/4411 (2013.01); G06F 13/4022 (2013.01); G06F 2009/45579 (2013.01);
Abstract

Methods and systems for I/O acceleration on a virtualized information handling system include loading a storage virtual appliance as a virtual machine on a hypervisor. The hypervisor may execute using a first processor and a second processor. The storage virtual appliance is accessed by the hypervisor using a PCI-E device driver that is mapped to a first PCI-E NTB logical endpoint at the first processor. A second PCI-E device driver may be loaded on the storage virtual appliance that accesses the hypervisor and is mapped to a second PCI-E NTB logical endpoint at the second processor. A data transfer operation may be executed between a first memory space that is mapped to the first PCI-E NTB logical endpoint and a second memory space that is mapped to the second PCI-E NTB logical endpoint. The data transfer operation may be a read or a write operation.


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