The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Dec. 22, 2011
Applicants:

Jack Hilaire Choquette, Palo Alto, CA (US);

Michael Fetterman, Boxborough, MA (US);

Shirish Gadre, Fremont, CA (US);

Xiaogang Qiu, San Jose, CA (US);

Omkar Paranjape, Austin, TX (US);

Anjana Rajendran, San Jose, CA (US);

Stewart Glenn Carlton, Madison, AL (US);

Eric Lyell Hill, Palo Alto, CA (US);

Rajeshwaran Selvanesan, Milpitas, CA (US);

Douglas J. Hahn, Los Altos, CA (US);

Inventors:

Jack Hilaire Choquette, Palo Alto, CA (US);

Michael Fetterman, Boxborough, MA (US);

Shirish Gadre, Fremont, CA (US);

Xiaogang Qiu, San Jose, CA (US);

Omkar Paranjape, Austin, TX (US);

Anjana Rajendran, San Jose, CA (US);

Stewart Glenn Carlton, Madison, AL (US);

Eric Lyell Hill, Palo Alto, CA (US);

Rajeshwaran Selvanesan, Milpitas, CA (US);

Douglas J. Hahn, Los Altos, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2006.01); G06F 9/30 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3851 (2013.01); G06F 9/3012 (2013.01);
Abstract

One embodiment of the present invention sets forth a technique for performing a shaped access of a register file that includes a set of N registers, wherein N is greater than or equal to two. The technique involves, for at least one thread included in a group of threads, receiving a request to access a first amount of data from each register in the set of N registers, and configuring a crossbar to allow the at least one thread to access the first amount of data from each register in the set of N registers.


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