The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Sep. 24, 2013
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

David A. Stronks, San Jose, CA (US);

Ahmad Al-Dahle, Santa Clara, CA (US);

Wei H. Yao, Palo Alto, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/044 (2006.01); G06F 3/041 (2006.01); G02F 1/1362 (2006.01); G09G 3/20 (2006.01); G09G 3/36 (2006.01); G02F 1/136 (2006.01);
U.S. Cl.
CPC ...
G06F 3/044 (2013.01); G02F 1/13624 (2013.01); G06F 3/0412 (2013.01); G06F 3/0416 (2013.01); G06F 3/0418 (2013.01); G09G 3/20 (2013.01); G02F 2001/13606 (2013.01); G06F 2203/04107 (2013.01); G09G 3/3655 (2013.01); G09G 2300/0847 (2013.01); G09G 2320/0209 (2013.01);
Abstract

Devices and methods for reducing display-to-touch crosstalk are provided. In or more examples, an electronic display panel may include a pixel. The pixel may include a pixel electrode, a common electrode, and a first transistor having a first source coupled to a data line, a first gate coupled to a gate line, and a first drain coupled to the pixel electrode. The pixel may also include a second transistor having a second source coupled to the common electrode, a second gate coupled to the gate line, and a second drain coupled to a common voltage source. The second transistor may be configured to cause a parasitic capacitance between the gate line and the second drain of the second transistor and to reduce an effect of a parasitic capacitance between the gate line and the first drain of the first transistor.


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