The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2017
Filed:
Mar. 25, 2015
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Hariprasad Thodukattil Thazhatheppattu, Bangalore, IN;
Prasant Vallur, Bangalore, IN;
Animesh Sharma, Bangalore, IN;
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A technique implements differential digital logic circuits with a differential clock distribution network using standard cell differential clock gater circuits to reduce area, delay, power consumption in integrated circuits. An apparatus includes a first terminal configured to receive a clock signal, a second terminal configured to receive a complementary clock signal, and a third terminal configured to receive a clock control signal. The apparatus includes a latch circuit configured to generate a latched version of the clock control signal based on a version of the clock control signal, a version of the clock signal, and a version of the complementary clock signal. The apparatus includes a combinatorial circuit configured to generate a gated clock signal and a gated complementary clock signal based on the version of the clock control signal, the version of the clock signal, and the version of the complementary clock signal.