The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2017

Filed:

Jan. 11, 2016
Applicant:

Oracle International Corporation, Redwood Shores, CA (US);

Inventors:

Suwen Yang, Mountain View, CA (US);

Frankie Y. Liu, Palo Alto, CA (US);

Vincent C. Lee, San Mateo, CA (US);

Assignee:

ORACLE INTERNATIONAL CORPORATION, Redwood Shores, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); H03L 7/06 (2006.01); H03K 5/05 (2006.01); H03L 7/091 (2006.01);
U.S. Cl.
CPC ...
H03K 5/05 (2013.01); H03L 7/091 (2013.01);
Abstract

In an integrated circuit, a resettable data latch and a second resettable data latch at ends of a pipeline in a frequency-comparison circuit receive input clocks. This pipeline operates asynchronously and includes at least a pair of flow-control elements separated by a NAND-gate detector circuit. Moreover, the resettable data latch and the second resettable data latch selectively generate tokens and spaces based on rising or falling edges of the input clocks. Then, the frequency-comparison circuit moves the tokens and the spaces in the pipeline between the ends based on a difference in fundamental frequencies of the input clocks. Furthermore, arbiter circuits in the frequency-comparison circuit provide output signals based on changes in numbers of tokens proximate to the ends, to indicate how at least one of the input clocks should be adjusted so that the fundamental frequencies converge on a common value.


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