The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9620527 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 11, 2017

Filed:

Apr. 17, 2015
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Hefei Boe Optoelectronics Technology Co., Ltd., Hefei, Anhui, CN;

Inventor:

Qiyu Shen, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/77 (2017.01); H01L 29/786 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1237 (2013.01); G02F 1/1362 (2013.01); G02F 1/1368 (2013.01); G02F 1/136286 (2013.01); H01L 21/77 (2013.01); H01L 27/12 (2013.01); H01L 27/124 (2013.01); H01L 27/1251 (2013.01); H01L 27/1262 (2013.01); H01L 29/786 (2013.01);
Abstract

An array substrate includes a base substrate () and a gate line () and a data line () provided on the base, the gate line () and the data line () define a pixel unit, and in the pixel unit, a thin film transistor () is provided, the thin film transistor () includes a gate electrode (), a gate insulation layer (), an active layer (), a source electrode () and a drain electrode (). The gate insulation layer () includes a first gate insulation portion () and a second gate insulation portion (), the gate electrode () is located between the first gate insulation portion () and the second gate insulation portion (), and the second gate insulation portion () is located between the gate electrode () and the active layer (). The array substrate further includes a conductive pad (), and a first via () corresponding to the conductive pad () is provided in the gate insulation layer () at both sides of the gate line (), and the data line () is connected to the conductive pad () through the first via (). The array substrate is capable of improving the definition, the resolution and the aperture ratio of a display device. A manufacturing method for an array substrate and a display device including such an array substrate are also disclosed.


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