The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2017

Filed:

Feb. 04, 2016
Applicant:

Japan Display Inc., Tokyo, JP;

Inventors:

Isao Suzumura, Tokyo, JP;

Norihiro Uemura, Tokyo, JP;

Hidekazu Miyake, Tokyo, JP;

Yohei Yamaguchi, Tokyo, JP;

Assignee:

Japan Display Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 21/473 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1225 (2013.01); H01L 21/02071 (2013.01); H01L 21/02164 (2013.01); H01L 21/02211 (2013.01); H01L 21/02274 (2013.01); H01L 21/32138 (2013.01); H01L 21/32139 (2013.01); H01L 21/473 (2013.01); H01L 27/127 (2013.01); H01L 27/1248 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78693 (2013.01);
Abstract

There is provided a bottom gate channel etched thin film transistor that can suppress initial Vth depletion and a Vth shift. A thin film transistor is formed, including a gate electrode interconnection disposed on a substrate, a gate insulating film, an oxide semiconductor layer to be a channel layer, a stacked film of a source electrode interconnection and a first hard mask layer, a stacked film of a drain electrode interconnection and a second hard mask layer, and a protective insulating film.


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