The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2017

Filed:

Feb. 24, 2016
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventor:

Hyun Ho Lee, Icheon-si, KR;

Assignee:

SK HYNIX INC., Icheon-Si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/28282 (2013.01);
Abstract

The present disclosure provides a method of manufacturing a three dimensional memory device to suppress warpage of conductive patterns. The method may include providing a multilayered structure in which different material layers are alternately stacked over a substrate, etching partially the material layers to form a multi-step structure, each step being formed of at least one pair of the material layers, forming vertical support layers, each support layer being disposed on a top face of each step, removing partially the material layers to form recesses, filling the recesses with a conductive material to form gate lines, the gate line defining an upper portion of the step, and forming vertical contact plugs respectively on the upper portion of the step.


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