The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2017

Filed:

Jun. 06, 2014
Applicant:

Cornell University, Ithaca, NY (US);

Inventors:

Michal Lipson, Ithaca, NY (US);

Yoon Ho Lee, Ithaca, NY (US);

Assignee:

CORNELL UNIVERSITY, Ithaca, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/12 (2006.01); H01L 25/16 (2006.01); H01L 27/144 (2006.01); H01L 25/00 (2006.01); H01L 31/0232 (2014.01); H01L 33/58 (2010.01); H01L 23/13 (2006.01);
U.S. Cl.
CPC ...
H01L 25/167 (2013.01); G02B 6/12004 (2013.01); G02B 6/12007 (2013.01); H01L 25/50 (2013.01); H01L 27/144 (2013.01); H01L 31/0232 (2013.01); H01L 33/58 (2013.01); H01L 23/13 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Techniques, systems, and devices are disclosed to provide multilayer platforms for integrating semiconductor integrated circuit dies, optical waveguides and photonic devices to provide intra-die or inter-die optical connectivity. For example, an integrated semiconductor device having integrated circuits respectively formed on different semiconductor integrated circuit dies is provided to include a carrier substrate structured to form openings on a top side of the carrier substrate; semiconductor integrated circuit dies fixed to bottom surfaces of the openings of the carrier substrate, each semiconductor integrated circuit die including a semiconductor substrate and an integrated circuit formed on the semiconductor substrate to include one or more circuit components, and each semiconductor integrated circuit die being structured to have a top surface substantially coplanar with the top side of the carrier substrate; and planar layers formed on top of the top surfaces of the semiconductor integrated circuit dies and the top side of the carrier substrate to include optical waveguides and photonic devices to provide (1) intra-die optical connectivity for photonic devices associated with a semiconductor integrated circuit die, or (2) inter-die optical connectivity for photonic devices associated with different semiconductor integrated circuit dies.


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