The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2017
Filed:
Jun. 06, 2016
Applicant:
Powerchip Technology Corporation, Hsinchu, TW;
Inventors:
Assignee:
Powerchip Technology Corporation, Hsinchu, TW;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 21/762 (2006.01); H01L 29/40 (2006.01); H01L 21/3105 (2006.01); H01L 27/088 (2006.01); H01L 27/11521 (2017.01); H01L 27/11531 (2017.01);
U.S. Cl.
CPC ...
H01L 21/28035 (2013.01); H01L 21/2815 (2013.01); H01L 21/31055 (2013.01); H01L 21/762 (2013.01); H01L 27/088 (2013.01); H01L 27/11521 (2013.01); H01L 27/11531 (2013.01); H01L 29/0649 (2013.01); H01L 29/401 (2013.01); H01L 29/4925 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01);
Abstract
A method for fabricating semiconductor device is disclosed. A substrate having a first gate layer and a first dielectric layer thereon is provided. A shallow trench isolation (STI) is formed in the substrate and surrounds the first gate layer and the first dielectric layer. The first dielectric layer is removed. A first spacer is formed on the sidewall of the STI above the first gate layer. Using the first spacer as mask, part of the first gate layer and part of the substrate are removed for forming a first opening while defining a first gate structure and a second gate structure.