The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2017

Filed:

Mar. 15, 2013
Applicant:

Synaptics Incorporated, Santa Clara, CA (US);

Inventors:

Jim Dunphy, San Jose, CA (US);

Robert J Bolender, Davis, CA (US);

Adam Schwartz, Redwood City, CA (US);

David Hoch, Los Gatos, CA (US);

Assignee:

Synaptics Incorporated, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/16 (2006.01); G06F 3/044 (2006.01);
U.S. Cl.
CPC ...
G06F 1/1692 (2013.01); G06F 3/044 (2013.01);
Abstract

A capacitive input device has a sensor electrode pattern disposed on a first side of a substrate. The sensor electrode pattern comprises a plurality of sensor electrode elements disposed on the first side of a first substrate. A plurality of routing traces is disposed along a first edge of the sensor electrode pattern on the first side of the substrate and configured to communicatively couple at least some of the sensor electrodes with a processing system. A pair of guard traces is disposed in the same layer as and brackets the plurality of routing traces. A guard overlaps the routing traces, is disposed proximate the routing traces on the first side of the substrate, and ohmically couples the pair of guard traces with one another. A second insulator is disposed between the routing traces and the guard. The second insulator and the first insulator are disposed in the same layer.


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