The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2017

Filed:

Oct. 20, 2015
Applicant:

Macau University of Science and Technology, Macau, MO;

Inventors:

Naiqi Wu, Macau, MO;

Yan Qiao, Macau, MO;

Mengchu Zhou, Macau, MO;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G05B 19/418 (2006.01); B25J 9/16 (2006.01); H01L 21/67 (2006.01); H01L 21/677 (2006.01); H01L 21/68 (2006.01);
U.S. Cl.
CPC ...
G05B 19/41885 (2013.01); B25J 9/1669 (2013.01); G05B 19/41865 (2013.01); H01L 21/67201 (2013.01); H01L 21/67742 (2013.01); H01L 21/68 (2013.01); G05B 2219/39536 (2013.01);
Abstract

Due to the trend of using larger wafer diameter and smaller lot size, cluster tools need to switch from processing one lot of wafers to another frequently. It leads to more transient periods in wafer fabrication. Their efficient scheduling and control problems become more and more important. It becomes difficult to solve such problems, especially when wafer residency time constraints must be considered. This work develops a Petri net model to describe the behavior during the start-up transient processes of a single-arm cluster tool. Then, based on the model, for the case that the difference of workloads among the steps is not too large and can be properly balanced, a scheduling algorithm to find an optimal feasible schedule for the start-up process is given. For other cases schedulable at the steady state, a linear programming model is developed to find an optimal feasible schedule for the start-up process.


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