The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2017

Filed:

Apr. 19, 2011
Applicants:

Florian Moliere, Paris, FR;

Sebastien Morand, Boulogne-Billancourt, FR;

Alexandre Douin, Nanterre, FR;

Gerard Salvaterra, Clamart, FR;

Christian Binois, Francourville, FR;

Daniel Peyre, St Remy les Chevreuse, FR;

Inventors:

Florian Moliere, Paris, FR;

Sebastien Morand, Boulogne-Billancourt, FR;

Alexandre Douin, Nanterre, FR;

Gerard Salvaterra, Clamart, FR;

Christian Binois, Francourville, FR;

Daniel Peyre, St Remy les Chevreuse, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2863 (2013.01); G01R 31/2874 (2013.01); G01R 31/2898 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01);
Abstract

Disclosed is in particular a device () for stressing an integrated circuit () including an electronic chip () mounted in a housing (), the device including a source () of thermal stress. The device () also includes a thermally conductive coupling member (), designed to be thermally coupled to the source () of thermal stress during the stressing operation. The coupling member () includes an end () whose geometry is suitable for being introduced into an aperture with a predefined geometry, to be made in the housing () of the integrated circuit () so as to thermally couple a coupling face () of this end () with a face () of the electronic chip ().


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