The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2017

Filed:

Jun. 13, 2016
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventor:

Abdullah Ahmed, Scarborough, CA;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 5/15 (2006.01); H03B 5/32 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/15 (2013.01); H03B 5/32 (2013.01); H03K 5/00006 (2013.01);
Abstract

A clock circuit includes an amplifier, an electrical supply, a feedback circuit, and a comparator. The amplifier has an input node and an output node that are coupled to a crystal to provide an internal clock signal on the output node at a specified frequency. The electrical supply source provides electrical power to the amplifier at a specified input voltage. The feedback circuit is coupled between the input node and the output node, and forms a low pass filter for attenuating the internally generated clock signal on the input node. The feedback circuit biases the input node at a direct current (DC) voltage level that is biased to be less than the specified input voltage. When an external clock signal is applied at the output node, the comparator generates a digital clock signal according to the external clock signal, and when no external clock signal is applied at the output, the comparator generates the digital clock signal according to the internal clock signal.


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