The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2017

Filed:

Sep. 24, 2014
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventor:

Zhongshan Hong, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/84 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 29/49 (2006.01); B82Y 10/00 (2011.01); B82Y 40/00 (2011.01); H01L 29/423 (2006.01); H01L 29/775 (2006.01); H01L 29/41 (2006.01); H01L 21/02 (2006.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0673 (2013.01); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01); H01L 21/265 (2013.01); H01L 29/413 (2013.01); H01L 29/4232 (2013.01); H01L 29/495 (2013.01); H01L 29/4916 (2013.01); H01L 29/4966 (2013.01); H01L 29/665 (2013.01); H01L 29/6659 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/775 (2013.01); H01L 29/78 (2013.01); H01L 21/02488 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 29/16 (2013.01); H01L 29/20 (2013.01);
Abstract

A method of manufacturing a nanowire device is disclosed. The method includes providing a substrate, wherein the substrate comprises a pair of support pads, a recess disposed between the support pads, a second insulating layer disposed on the support pads, a third insulating layer disposed on a bottom of the recess, and at least one nanowire suspended between the support pads at a top portion of the recess; forming a first insulating layer on the nanowire; depositing a dummy gate material over the substrate on the first insulating layer, and patterning the dummy gate material to form a dummy gate structure surrounding a channel region; forming a first oxide layer on laterally opposite sidewalls of the dummy gate; and extending the nanowire on laterally opposite ends of the channel region to the respective support pads, so as to form a source region and a drain region.


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