The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2017
Filed:
Dec. 28, 2015
Applicant:
SK Hynix Inc., Icheon-Si, KR;
Inventors:
Kwan-Woo Do, Icheon-Si, KR;
Ki-Seon Park, Icheon-Si, KR;
Assignee:
SK hynix Inc., Icheon-Si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 27/24 (2006.01); H01L 27/22 (2006.01); H01L 43/08 (2006.01); H01L 45/00 (2006.01); H01L 43/02 (2006.01); G11C 13/00 (2006.01); H01L 27/105 (2006.01);
U.S. Cl.
CPC ...
H01L 27/249 (2013.01); G11C 13/0004 (2013.01); G11C 13/0021 (2013.01); H01L 27/222 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 27/1052 (2013.01); H01L 27/115 (2013.01); H01L 45/04 (2013.01);
Abstract
An electronic device includes a semiconductor memory that includes: an inter-layer dielectric layer which is formed over a substrate; a contact plug which is coupled with the substrate by passing through the inter-layer dielectric layer and has a protruding portion over the inter-layer dielectric layer; a first variable resistance pattern which is formed over the contact plug; and a protective layer which covers the first variable resistance pattern and a portion of sidewalls of the contact plug in such a manner that the sidewalls of the contact plug are exposed.