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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9613981 B1

PDFFull Text
Date of Patent:
Apr. 04, 2017

Filed:

Jul. 19, 2016

Vertical channel-type 3d semiconductor memory device and method for manufacturing the same

Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Zongliang Huo, Beijing, CN;

Ming Liu, Beijing, CN;

Assignee:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Attorney:

Knobbe, Martens, Olson & Bear, LLP

Primary Examiner:

Jarrett Stark

Assistant Examiner:

Shahed Ahmed

Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11582 (2017.01); H01L 21/764 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 27/1157 (2017.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 27/11519 (2017.01); H01L 27/11565 (2017.01); H01L 29/04 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/20 (2006.01); H01L 29/201 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 21/3213 (2006.01); H01L 21/324 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0217 (2013.01); H01L 21/02181 (2013.01); H01L 21/02532 (2013.01); H01L 21/02546 (2013.01); H01L 21/02592 (2013.01); H01L 21/02595 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 21/31111 (2013.01); H01L 21/324 (2013.01); H01L 21/32133 (2013.01); H01L 21/764 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 29/04 (2013.01); H01L 29/0649 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01); H01L 29/20 (2013.01); H01L 29/201 (2013.01); H01L 29/4916 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/7883 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01); H01L 21/02667 (2013.01);
Abstract

A vertical channel-type 3D semiconductor memory device and a method for manufacturing the same are disclosed. In one aspect, the method includes depositing alternating insulating and electrode layers on a substrate to form a multi-layer film. The method further includes etching the film to the substrate to form through-holes, each of which defines a channel region. The method further includes depositing barrier, storage, and tunnel layers in sequence on inner walls of through-holes to form gate stacks. The method further includes depositing and incompletely filling a channel material on a surface of the tunnel layer of gate stacks to form a hollow channels. The method further includes forming drains in contact hole regions for bit-line connection in top portions of the hollow channels. The method further includes forming sources in contact regions between the through-holes and the substrate in bottom portions of the hollow channels.

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