The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2017
Filed:
Mar. 10, 2016
Applicant:
Kabushika Kaisha Toshiba, Tokyo, JP;
Inventor:
Yoshiki Kamata, Ibaraki, JP;
Assignee:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0376 (2006.01); H01L 29/10 (2006.01); H01L 29/768 (2006.01); H01L 29/76 (2006.01); H01L 27/092 (2006.01); H01L 29/786 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 29/04 (2006.01); H01L 29/16 (2006.01); H01L 29/165 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/22 (2006.01); H01L 29/225 (2006.01); H01L 29/24 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/845 (2013.01); H01L 27/1211 (2013.01); H01L 29/04 (2013.01); H01L 29/1604 (2013.01); H01L 29/165 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/2006 (2013.01); H01L 29/225 (2013.01); H01L 29/2206 (2013.01); H01L 29/247 (2013.01); H01L 29/786 (2013.01);
Abstract
According to one embodiment, a field-effect transistor includes a source region of a first conductivity type, a drain region of the first conductivity type and a channel region of the first conductivity type between the source region and the drain region, the source region, the drain region and the channel region being disposed in a polycrystalline semiconductor layer; a first layer including an amorphous semiconductor layer disposed on the channel region; a gate insulating layer disposed on the first layer; and a gate electrode disposed on the gate insulating layer.