The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2017

Filed:

Jan. 17, 2014
Applicant:

Sumitomo Electric Industries, Ltd., Osaka-shi, JP;

Inventors:

Taku Horii, Osaka, JP;

Masaki Kijima, Itami, JP;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/04 (2006.01); H01L 29/66 (2006.01); H01L 29/16 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/324 (2006.01); H01L 29/06 (2006.01); H01L 21/033 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0455 (2013.01); H01L 21/0217 (2013.01); H01L 21/0223 (2013.01); H01L 21/02123 (2013.01); H01L 21/02164 (2013.01); H01L 21/02255 (2013.01); H01L 21/02271 (2013.01); H01L 21/0332 (2013.01); H01L 21/046 (2013.01); H01L 21/0465 (2013.01); H01L 21/31144 (2013.01); H01L 21/324 (2013.01); H01L 29/0619 (2013.01); H01L 29/1608 (2013.01); H01L 29/66053 (2013.01); H01L 29/66068 (2013.01); H01L 29/7827 (2013.01);
Abstract

A method of manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first mask layer is formed in contact with a first main surface of the silicon carbide substrate. The first mask layer includes a first layer disposed in contact with the first main surface, an etching stop layer disposed in contact with the first layer and made of a material different from that for the first layer, and a second layer disposed in contact with a surface of the etching stop layer opposite to the surface in contact with the first layer. A recess is formed in the first mask layer by etching the second layer and the etching stop layer. A first impurity region is formed in the silicon carbide substrate using the first mask layer with the recess. The first mask layer does not include a metallic element.


Find Patent Forward Citations

Loading…