The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2017

Filed:

Mar. 03, 2016
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Kouichirou Yamaguchi, Kawasaki, JP;

Makoto Miakashi, Kawasaki, JP;

Hitoshi Shiga, Kawasaki, JP;

Noboru Shibata, Kawasaki, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/02 (2006.01); G11C 29/24 (2006.01); G11C 11/406 (2006.01); G11C 16/00 (2006.01); G11C 16/34 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 29/76 (2013.01); G11C 11/406 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 29/24 (2013.01); G11C 16/00 (2013.01); G11C 16/349 (2013.01); G11C 2029/4402 (2013.01);
Abstract

A semiconductor storage device has a memory cell array, a plurality of word lines, a plurality of bit lines, and a plurality of blocks including a group of at least some memory cells, a defect information storage block that stores defect information in the memory cell array, a first defect detection circuitry that reads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is a defect in the defect information storage block, a second defect detection circuitry that changes a read voltage level for reading the data of the memory cells, rereads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is the defect in the defect information storage block, and a defect determination circuitry that determines the defect information storage block as a defective block.


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