Self-selecting local bit line for a three-dimensional memory array

Abstract

A three-dimensional memory device includes an alternating stack of word lines and insulating layers, a plurality of gate lines, a plurality of global bit lines, and a plurality of local bit lines contacting a respective gate line and global bit line. A plurality of memory elements is located at each overlap region between the word lines and the local bit lines. A plurality of diodes located in electrical series between each of the local bit lines and the respective one of the plurality of gate lines. A plurality of selector elements located in electrical series between each of the local bit lines and the respective one of the plurality of global bit lines. The plurality of selector elements includes a material that provides a conductivity change of at least one order of magnitude upon application of a voltage.