The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2017

Filed:

Nov. 10, 2015
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventor:

Jin Hee Cho, Cheongju-si, KR;

Assignee:

SK HYNIX INC., Icheon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 11/4091 (2006.01); G11C 5/06 (2006.01); G11C 11/4096 (2006.01); G11C 11/408 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4091 (2013.01); G11C 5/063 (2013.01); G11C 11/4087 (2013.01); G11C 11/4096 (2013.01);
Abstract

Semiconductor devices capable of a sensing margin of a semiconductor device are described. A semiconductor device may include a plurality of mats, a plurality of sensing circuits, a plurality of connecting circuits, and a plurality of mat dividing circuits. The mats are divided into upper regions and lower regions and activated by word lines. The sensing circuits are arranged in regions among the plurality of mats and are configured to sense/amplify data applied from the plurality of mats. The connecting circuits are configured to control connections between the mats and the sensing circuits in correspondence to a plurality of bit line selection signals. The mat dividing circuits are configured to selectively connect bit lines of the upper regions and the lower regions to each other in correspondence to a plurality of mat selection signals.


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