The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2017

Filed:

Sep. 18, 2013
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Kevin Wong, San Jose, CA (US);

Craig Ross, Santa Clara, CA (US);

Thomas Dewey, Menlo Park, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 1/00 (2006.01); G06F 13/42 (2006.01); G06F 1/32 (2006.01); G06F 13/364 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4291 (2013.01); G06F 1/3203 (2013.01); G06F 13/364 (2013.01); G06F 2213/0016 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1235 (2013.01);
Abstract

Systems and devices configured to implement techniques for ensuring the completion of transactions while minimizing latency and power consumption are described. A device may be operably coupled to a bidirectional communications bus. A bidirectional communications bus may include a clock line and a data line. The device may be configured to determine if an initiated transaction corresponds to a device in a low power state. The device may pause the transaction. The device may replay portions of the transaction when the device is in an appropriate power state. The device may replay portions of the transaction using an override interface.


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