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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9612931 B1

PDFFull Text
Date of Patent:
Apr. 04, 2017

Filed:

Jun. 04, 2014

System and method for synchronously controlling led on multiple control modules based on a register synchronized with synchronous packets

Applicant:

Hitachi, Ltd., Tokyo, JP;

Inventors:

Akihiro Umezawa, Tokyo, JP;

Nobuo Yagi, Tokyo, JP;

Kazuki Sato, Tokyo, JP;

Assignee:

HITACHI, LTD., Tokyo, JP;

Attorney:

Volpe and Koenig, P.C.

Primary Examiner:

Xuxing Chen

Int. Cl.
CPC ...
G06F 1/04 (2006.01); G06F 15/16 (2006.01); G06F 1/12 (2006.01); G06F 11/32 (2006.01); G06F 17/50 (2006.01); H04N 13/02 (2006.01); H04N 13/00 (2006.01); H04N 21/633 (2011.01); H04N 21/647 (2011.01); G06F 13/42 (2006.01); H04N 21/43 (2011.01); G06F 11/30 (2006.01);
U.S. Cl.
CPC ...
G06F 11/325 (2013.01); G05B 2219/31213 (2013.01); G06F 11/3031 (2013.01); G06F 11/3058 (2013.01); G06F 13/4243 (2013.01); G06F 17/5027 (2013.01); G06F 17/5054 (2013.01); H04N 13/0051 (2013.01); H04N 13/0296 (2013.01); H04N 21/4302 (2013.01); H04N 21/633 (2013.01); H04N 21/64746 (2013.01);
Abstract

In an information processing system, plural information processing devices are mutually connected by an SMP connection mechanism. Each of the information processing devices includes a control device (FPGA) having a synchronous register that shows the state of a control signal of the information processing device and an internode communication access control unit that transmits first synchronous packets with the content of the synchronous register reflected to the other information processing devices at predetermined time intervals, receives second synchronous packets from the other information processing devices, and reflects the content of the received second synchronous packets on the synchronous register.

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