The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2017

Filed:

Sep. 03, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Wen Gu, Tianjin, CN;

Jing Cui, Tianjin, CN;

Shayan Zhang, Cedar Park, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 9/44 (2006.01); G06F 1/24 (2006.01); G06F 1/30 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3296 (2013.01); G06F 1/24 (2013.01); G06F 1/30 (2013.01); G06F 1/324 (2013.01); G06F 1/3206 (2013.01); G06F 1/3243 (2013.01); G06F 9/4418 (2013.01);
Abstract

An integrated circuit (IC) and associated method support using a pre-use configuration for determining an initial/preferred operational mode for the IC from plural operational modes that may be entered following power-up cycles of the IC. The initial/preferred operational mode can be determined after the design phase of the IC so that, during IC operation, wasted power or delay are not incurred by first requiring that the IC power up in a default operational mode and subsequently run executive code to reprogram the IC to enter an operational mode that is preferred for the application for which the IC is being used by the IC integrator/user. The configurations determine clock frequencies and/or power levels for core processing and/or peripheral modules and allow the same IC design/die to be targeted to a spectrum of different power usage/performance applications by the integrator/user.


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