The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2017

Filed:

Aug. 08, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Dexter Chun, San Diego, CA (US);

Yanru Li, San Diego, CA (US);

Alex Tu, San Diego, CA (US);

Haw-Jing Lo, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 1/32 (2006.01); G06F 12/06 (2006.01); G11C 14/00 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3275 (2013.01); G06F 12/0607 (2013.01); G11C 14/0009 (2013.01); G06F 2212/1028 (2013.01);
Abstract

Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method involves configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively lower power use cases. Memory requests are received from one or more clients. The memory requests comprise a preference for power savings or performance. Received memory requests are assigned to the linear region or the interleaved region according to the preference for power savings or performance.


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