The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9609744 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 28, 2017

Filed:

Mar. 24, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Mark K. Hoffmeyer, Rochester, MN (US);

Amanda E. Mikhail, Rochester, MN (US);

Arvind K. Sinha, Los Alamos, NM (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H05K 1/11 (2006.01); H05K 3/00 (2006.01); H05K 1/02 (2006.01); H05K 3/34 (2006.01); H05K 1/18 (2006.01); G01R 31/26 (2014.01);
U.S. Cl.
CPC ...
H05K 1/0271 (2013.01); G06F 17/5068 (2013.01); G06F 17/5072 (2013.01); G06F 17/5081 (2013.01); H05K 1/11 (2013.01); H05K 1/181 (2013.01); H05K 3/3436 (2013.01); G01R 31/26 (2013.01); G06F 2217/12 (2013.01); G06F 2217/14 (2013.01); G06F 2217/38 (2013.01); G06F 2217/40 (2013.01); G06F 2217/80 (2013.01); H05K 3/3494 (2013.01); H05K 2201/09136 (2013.01); H05K 2201/10734 (2013.01); Y02P 70/613 (2015.11);
Abstract

Printed circuit boards (PCBs) can be designed to have dynamic warp characteristics complimentary to those of an attached component. A PCB and an attached component can be designed to dynamically warp, during a thermal excursion, in the same direction and with approximately the same magnitude of warp. Warp characteristics of the PCB and the attached component can be determined by the vertical thickness of conductor and dielectric layers, by the wiring density and number of conductor layers. Warp characteristics can also be at least partially determined by the arrangement/ordering of conductor and dielectric layers, by dimensions of a sash structure surrounding a component outline and by dimensions of a prepreg layer applied to an existing design. Such a prepreg layer can cover a portion or an entirety of one of the PCBs planar surfaces.


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