The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

May. 23, 2008
Applicants:

Orly Yadid-pecht, Haifa, IL;

Terence Tam, Calgary, CA;

Graham Jullien, Tecumseh, CA;

Inventors:

Orly Yadid-Pecht, Haifa, IL;

Terence Tam, Calgary, CA;

Graham Jullien, Tecumseh, CA;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H04N 5/357 (2011.01); H04N 5/353 (2011.01); H04N 5/355 (2011.01); H04N 5/363 (2011.01); H04N 5/365 (2011.01); H04N 5/374 (2011.01); H04N 5/3745 (2011.01); H04N 5/378 (2011.01);
U.S. Cl.
CPC ...
H04N 5/3575 (2013.01); H04N 5/3532 (2013.01); H04N 5/3559 (2013.01); H04N 5/363 (2013.01); H04N 5/365 (2013.01); H04N 5/378 (2013.01); H04N 5/3742 (2013.01); H04N 5/3745 (2013.01);
Abstract

Systems, methods, and apparatuses that may be employed to reduce noise in an electronic circuit are described. Systems are provided that include a circuit, wherein the circuit is configured to provide an active reset technique and an active column sensor readout technique. Methods for reducing circuit noise are also provided. The methods include providing a circuit configured to perform an active reset technique and an active column sensor readout technique. The methods further provide that the active reset technique and the active column sensor readout technique are both performed by the circuit. An imaging apparatus is provided that includes an array of photo-sensitive pixels, wherein each of the pixels can include a circuit configured to provide an active reset technique and an active column sensor readout technique. The active reset technique and the active column sensor readout technique are executable on the circuit.


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